Merge pull request #3337 from JerryImMouse/syntax-vhdl

Add syntax highlighting for VHDL language

.gitmodules

@@ -275,3 +275,6 @@
 [submodule "assets/themes/Catppuccin"]
 	path = assets/themes/Catppuccin
 	url = https://github.com/SchweGELBin/catppuccin-bat-sub.git
+[submodule "assets/syntaxes/02_Extra/SmartVHDL"]
+	path = assets/syntaxes/02_Extra/SmartVHDL
+	url = https://github.com/TheClams/SmartVHDL

CHANGELOG.md

@@ -38,6 +38,7 @@
 - Update quadlet syntax mapping rules to cover quadlets in subdirectories #3299 (@cyqsimon)
 - Add syntax Typst #3300 (@cskeeters)
 - Map `.mill` files to Scala syntax for Mill build tool configuration files #3311 (@krikera)
+- Add syntax highlighting for VHDL, see #3337 (@JerryImMouse)
 - Add syntax mapping for certbot certificate configuration #3338 (@cyqsimon)
 
 ## Themes

tests/syntax-tests/highlighted/VHDL/test.vhdl

@@ -0,0 +1,74 @@
+-- This is a single-line comment
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity SyntaxTest is
+    generic (
+        DATA_WIDTH : integer := 8
+    );
+    port (
+        clk     : in  std_logic;
+        rst     : in  std_logic;
+        a, b    : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+        sel     : in  std_logic;
+        result  : out std_logic_vector(DATA_WIDTH - 1 downto 0);
+        flag    : out std_logic
+    );
+end SyntaxTest;
+
+architecture Behavioral of SyntaxTest is
+
+    signal tmp : std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal done : std_logic := '0';
+
+    type state_type is (IDLE, LOAD, EXECUTE, DONE);
+    signal state : state_type := IDLE;
+
+begin
+
+    process(clk, rst)
+        variable i : integer := 0;
+    begin
+        if rst = '1' then
+            tmp   <= (others => '0');
+            flag  <= '0';
+            state <= IDLE;
+
+        elsif rising_edge(clk) then
+            case state is
+                when IDLE =>
+                    if sel = '1' then
+                        tmp <= a and b;
+                        state <= EXECUTE;
+                    else
+                        tmp <= a or b;
+                        state <= LOAD;
+                    end if;
+
+                when LOAD =>
+                    tmp <= a xor b;
+                    state <= EXECUTE;
+
+                when EXECUTE =>
+                    if i < DATA_WIDTH then
+                        tmp(i) <= not tmp(i);
+                        i := i + 1;
+                    else
+                        state <= DONE;
+                    end if;
+
+                when DONE =>
+                    flag <= '1';
+                    state <= IDLE;
+
+                when others =>
+                    state <= IDLE;
+            end case;
+        end if;
+    end process;
+
+    result <= tmp;
+
+end Behavioral;

tests/syntax-tests/source/VHDL/test.vhdl

@@ -0,0 +1,74 @@
+-- This is a single-line comment
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity SyntaxTest is
+    generic (
+        DATA_WIDTH : integer := 8
+    );
+    port (
+        clk     : in  std_logic;
+        rst     : in  std_logic;
+        a, b    : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+        sel     : in  std_logic;
+        result  : out std_logic_vector(DATA_WIDTH - 1 downto 0);
+        flag    : out std_logic
+    );
+end SyntaxTest;
+
+architecture Behavioral of SyntaxTest is
+
+    signal tmp : std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal done : std_logic := '0';
+
+    type state_type is (IDLE, LOAD, EXECUTE, DONE);
+    signal state : state_type := IDLE;
+
+begin
+
+    process(clk, rst)
+        variable i : integer := 0;
+    begin
+        if rst = '1' then
+            tmp   <= (others => '0');
+            flag  <= '0';
+            state <= IDLE;
+
+        elsif rising_edge(clk) then
+            case state is
+                when IDLE =>
+                    if sel = '1' then
+                        tmp <= a and b;
+                        state <= EXECUTE;
+                    else
+                        tmp <= a or b;
+                        state <= LOAD;
+                    end if;
+
+                when LOAD =>
+                    tmp <= a xor b;
+                    state <= EXECUTE;
+
+                when EXECUTE =>
+                    if i < DATA_WIDTH then
+                        tmp(i) <= not tmp(i);
+                        i := i + 1;
+                    else
+                        state <= DONE;
+                    end if;
+
+                when DONE =>
+                    flag <= '1';
+                    state <= IDLE;
+
+                when others =>
+                    state <= IDLE;
+            end case;
+        end if;
+    end process;
+
+    result <= tmp;
+
+end Behavioral;