Mohamed Abdelnour c18afcb01a Add Verilog syntax test file

2021-06-01 22:36:56 +02:00

..

highlighted

Add Verilog syntax test file

2021-06-01 22:36:56 +02:00

source

Add Verilog syntax test file

2021-06-01 22:36:56 +02:00

compare_highlighted_versions.py

Add comparison script

2020-08-03 15:59:53 +02:00

create_highlighted_versions.py

Add 'NOTICE' to list of file names to skip

2021-06-01 22:36:56 +02:00

regression_test.sh

Fix #1443 macOS: regression_test.sh: mktemp: illegal option (#1444)

2020-12-21 08:16:49 +01:00

update.sh

fix: warnings of ShellCheck

2020-12-21 09:08:54 +01:00