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CUDA: fix 1D im2col, add tests (ggml/993)
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@ -3141,7 +3141,6 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g
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case GGML_OP_ROPE:
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case GGML_OP_ROPE:
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return ggml_is_contiguous(op->src[0]);
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return ggml_is_contiguous(op->src[0]);
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case GGML_OP_IM2COL:
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case GGML_OP_IM2COL:
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return op->src[0]->type == GGML_TYPE_F16;
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case GGML_OP_POOL_2D:
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case GGML_OP_POOL_2D:
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case GGML_OP_SUM:
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case GGML_OP_SUM:
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case GGML_OP_SUM_ROWS:
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case GGML_OP_SUM_ROWS:
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@ -91,9 +91,9 @@ void ggml_cuda_op_im2col(ggml_backend_cuda_context & ctx, ggml_tensor * dst) {
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const int64_t OH = is_2D ? dst->ne[2] : 1;
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const int64_t OH = is_2D ? dst->ne[2] : 1;
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const int64_t OW = dst->ne[1];
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const int64_t OW = dst->ne[1];
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const size_t delta_offset = src1->nb[is_2D ? 2 : 1] / 4; // nb is byte offset, src is type float32
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const size_t delta_offset = src1->nb[is_2D ? 2 : 1] / 4; // nb is byte offset, src is type float32
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const int64_t batch = src1->ne[3];
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const int64_t batch = src1->ne[is_2D ? 3 : 2];
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const size_t batch_offset = src1->nb[3] / 4; // nb is byte offset, src is type float32
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const size_t batch_offset = src1->nb[is_2D ? 3 : 2] / 4; // nb is byte offset, src is type float32
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if(dst->type == GGML_TYPE_F16) {
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if(dst->type == GGML_TYPE_F16) {
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im2col_cuda_f16(src1_d, (half *) dst_d, IW, IH, OW, OH, KW, KH, IC, batch, batch_offset, delta_offset, s0, s1, p0, p1, d0, d1, stream);
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im2col_cuda_f16(src1_d, (half *) dst_d, IW, IH, OW, OH, KW, KH, IC, batch, batch_offset, delta_offset, s0, s1, p0, p1, d0, d1, stream);
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