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CUDA: MMQ code deduplication + iquant support (llama/8495)
* CUDA: MMQ code deduplication + iquant support * 1 less parallel job for CI build
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@ -59,6 +59,24 @@ void ggml_cuda_op_mul_mat_q(
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case GGML_TYPE_Q6_K:
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mul_mat_q_case<GGML_TYPE_Q6_K>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ2_XXS:
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mul_mat_q_case<GGML_TYPE_IQ2_XXS>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ2_XS:
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mul_mat_q_case<GGML_TYPE_IQ2_XS>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ2_S:
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mul_mat_q_case<GGML_TYPE_IQ2_S>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ3_XXS:
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mul_mat_q_case<GGML_TYPE_IQ3_XXS>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ3_S:
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mul_mat_q_case<GGML_TYPE_IQ3_S>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ1_S:
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mul_mat_q_case<GGML_TYPE_IQ1_S>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ4_XS:
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mul_mat_q_case<GGML_TYPE_IQ4_XS>(ctx, args, stream);
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break;
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@ -93,6 +111,12 @@ bool ggml_cuda_should_use_mmq(enum ggml_type type, int cc, int64_t ne11) {
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case GGML_TYPE_Q4_K:
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case GGML_TYPE_Q5_K:
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case GGML_TYPE_Q6_K:
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case GGML_TYPE_IQ2_XXS:
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case GGML_TYPE_IQ2_XS:
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case GGML_TYPE_IQ2_S:
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case GGML_TYPE_IQ3_XXS:
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case GGML_TYPE_IQ3_S:
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case GGML_TYPE_IQ1_S:
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case GGML_TYPE_IQ4_XS:
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case GGML_TYPE_IQ4_NL:
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mmq_supported = true;
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File diff suppressed because it is too large
Load Diff
@ -23,7 +23,8 @@ SOURCE_FATTN_WMMA_CASE = "DECL_FATTN_WMMA_F16_CASE({head_size}, {cols_per_block}
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TYPES_MMQ = [
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"GGML_TYPE_Q4_0", "GGML_TYPE_Q4_1", "GGML_TYPE_Q5_0", "GGML_TYPE_Q5_1", "GGML_TYPE_Q8_0",
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"GGML_TYPE_Q2_K", "GGML_TYPE_Q3_K", "GGML_TYPE_Q4_K", "GGML_TYPE_Q5_K", "GGML_TYPE_Q6_K",
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"GGML_TYPE_IQ4_NL", "GGML_TYPE_IQ4_XS"
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"GGML_TYPE_IQ2_XXS", "GGML_TYPE_IQ2_XS", "GGML_TYPE_IQ2_S", "GGML_TYPE_IQ3_XXS", "GGML_TYPE_IQ3_S",
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"GGML_TYPE_IQ1_S", "GGML_TYPE_IQ4_NL", "GGML_TYPE_IQ4_XS"
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]
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SOURCE_MMQ = """// This file has been autogenerated by generate_cu_files.py, do not edit manually.
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@ -0,0 +1,5 @@
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// This file has been autogenerated by generate_cu_files.py, do not edit manually.
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#include "../mmq.cuh"
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DECL_MMQ_CASE(GGML_TYPE_IQ1_S);
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@ -0,0 +1,5 @@
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// This file has been autogenerated by generate_cu_files.py, do not edit manually.
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#include "../mmq.cuh"
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DECL_MMQ_CASE(GGML_TYPE_IQ2_S);
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@ -0,0 +1,5 @@
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// This file has been autogenerated by generate_cu_files.py, do not edit manually.
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#include "../mmq.cuh"
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DECL_MMQ_CASE(GGML_TYPE_IQ2_XS);
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@ -0,0 +1,5 @@
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// This file has been autogenerated by generate_cu_files.py, do not edit manually.
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#include "../mmq.cuh"
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DECL_MMQ_CASE(GGML_TYPE_IQ2_XXS);
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@ -0,0 +1,5 @@
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// This file has been autogenerated by generate_cu_files.py, do not edit manually.
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#include "../mmq.cuh"
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DECL_MMQ_CASE(GGML_TYPE_IQ3_S);
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@ -0,0 +1,5 @@
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// This file has been autogenerated by generate_cu_files.py, do not edit manually.
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#include "../mmq.cuh"
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DECL_MMQ_CASE(GGML_TYPE_IQ3_XXS);
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@ -188,6 +188,27 @@ template <int vdr> static __device__ __forceinline__ float vec_dot_q8_1_q8_1_imp
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return sumi*d8d8 + m8s8 / (QI8_1 / vdr);
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}
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template <int vdr> static __device__ __forceinline__ float vec_dot_q8_0_16_q8_1_impl(
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const int * v, const int * u, const float * d8_0, const float & d8_1) {
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float sumf = 0.0f;
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#pragma unroll
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for (int i0 = 0; i0 < vdr; i0 += QI8_0/2) {
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int sumi = 0;
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#pragma unroll
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for (int i = i0; i < i0 + QI8_0/2; ++i) {
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// SIMD dot product of quantized values
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sumi = ggml_cuda_dp4a(v[i], u[i], sumi);
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}
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sumf += d8_0[i0/(QI8_0/2)]*sumi;
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}
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return d8_1*sumf;
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}
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#define VDR_Q2_K_Q8_1_MMVQ 1
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#define VDR_Q2_K_Q8_1_MMQ 4
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