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CUDA: fix MMQ for non-contiguous src0, add tests (llama/10021)
* CUDA: fix MMQ for non-contiguous src0, add tests * revise test code
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@ -1151,8 +1151,8 @@ static cudaError_t ggml_cuda_cpy_tensor_2d(
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void * dst, const struct ggml_tensor * src, int64_t i3, int64_t i2, int64_t i1_low, int64_t i1_high, cudaStream_t stream) {
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GGML_ASSERT(ggml_backend_buffer_is_cuda(src->buffer));
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char * src_ptr = (char *) src->data;
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char * dst_ptr = (char *) dst;
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const char * src_ptr = (const char *) src->data;
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char * dst_ptr = (char *) dst;
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const int64_t ne0 = src->ne[0];
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const int64_t nb0 = src->nb[0];
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@ -1162,7 +1162,7 @@ static cudaError_t ggml_cuda_cpy_tensor_2d(
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const enum ggml_type type = src->type;
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const int64_t ts = ggml_type_size(type);
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const int64_t bs = ggml_blck_size(type);
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int64_t i1_diff = i1_high - i1_low;
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const int64_t i1_diff = i1_high - i1_low;
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const char * x = src_ptr + i1_low*nb1 + i2*nb2 + i3*nb3;
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if (nb0 == ts && nb1 == ts*ne0/bs) {
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@ -1479,13 +1479,17 @@ static void ggml_cuda_op_mul_mat(
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if (src0_is_contiguous) {
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dev[id].src0_dd = split ? (char *) src0_extra->data_device[id] : (char *) src0->data;
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} else {
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dev[id].src0_dd = dev[id].src0_dd_alloc.alloc(ctx.pool(id), ggml_nbytes(src0));
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// If src0 is not contiguous it will be copied to a temporary buffer, it may then be necessary to clear padding.
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const size_t nbytes_data = ggml_nbytes(src0);
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const size_t nbytes_padding = ggml_row_size(src0->type, MATRIX_ROW_PADDING - ne00 % MATRIX_ROW_PADDING);
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dev[id].src0_dd = dev[id].src0_dd_alloc.alloc(ctx.pool(id), nbytes_data + nbytes_padding);
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CUDA_CHECK(cudaMemsetAsync(dev[id].src0_dd + nbytes_data , 0, nbytes_padding, stream));
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}
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// If src0 is on a temporary compute buffers (partial offloading) there may be some padding that needs to be cleared:
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// If src0 is on a temporary compute buffer (partial offloading) there may be some padding that needs to be cleared:
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if (ne00 % MATRIX_ROW_PADDING != 0 && ggml_is_quantized(src0->type) && ggml_backend_buffer_get_usage(src0->buffer) == GGML_BACKEND_BUFFER_USAGE_COMPUTE && src0->view_src == nullptr) {
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const int64_t nbytes_data = ggml_row_size(src0->type, (dev[id].row_high - dev[id].row_low)*ne00);
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const int64_t nbytes_padding = ggml_row_size(src0->type, MATRIX_ROW_PADDING - ne00 % MATRIX_ROW_PADDING);
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const size_t nbytes_data = ggml_row_size(src0->type, (dev[id].row_high - dev[id].row_low)*ne00);
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const size_t nbytes_padding = ggml_row_size(src0->type, MATRIX_ROW_PADDING - ne00 % MATRIX_ROW_PADDING);
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CUDA_CHECK(cudaMemsetAsync(dev[id].src0_dd + nbytes_data , 0, nbytes_padding, stream));
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}
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@ -8,8 +8,6 @@ void ggml_cuda_op_mul_mat_q(
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const int64_t ne00 = src0->ne[0];
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const int64_t nb01 = src0->nb[1];
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const int64_t ne10 = src1->ne[0];
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const int64_t ne11 = src1->ne[1];
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GGML_ASSERT(ne10 % QK8_1 == 0);
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@ -17,7 +15,7 @@ void ggml_cuda_op_mul_mat_q(
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const int64_t ne0 = dst->ne[0];
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const int64_t row_diff = row_high - row_low;
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const int64_t stride00 = nb01 / ggml_type_size(src0->type);
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const int64_t stride00 = ne00 / ggml_blck_size(src0->type);
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int id = ggml_cuda_get_device();
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const int compute_capability = ggml_cuda_info().devices[id].cc;
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@ -3464,7 +3464,7 @@ int64_t ggml_nrows(const struct ggml_tensor * tensor) {
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size_t ggml_nbytes(const struct ggml_tensor * tensor) {
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size_t nbytes;
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size_t blck_size = ggml_blck_size(tensor->type);
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const size_t blck_size = ggml_blck_size(tensor->type);
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if (blck_size == 1) {
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nbytes = ggml_type_size(tensor->type);
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for (int i = 0; i < GGML_MAX_DIMS; ++i) {
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